Expeditiously providing best PPAL(Power, Performance, Area & Leakage key metrics in SOC/ASIC design), is the biggest challenge in VLSI. This challenge is ably met by the combination of DXCorr's highly optimized physical IPs, specific custom blocks and their physical design teams. "Rather than a generic solution, the client's IP should be as unique as their design. We build exactly what is needed to win their market. We tailor our solutions to exceed expectations," asserts Nirmalya, CEO, DXCorr.

DXCorr develops various inhouse tools that push the boundaries of the design process. Their design philosophy combines the potential of Computer Aided Design with the algorithmic nature of IP development. With inhouse software that expedites layout generation and a design team targeting best PPAL using proprietary algorithms to reduce iteration cycles, DXCorr delivers the industry's best custom physical IP solutions across various process nodes.

The Advanced Portfolio
The portfolio covers physical IP blocks such as SRAMs, MRAMs(STT & SOT), Standard Cells & I/Os accounting for most of the building blocks of SoC design. Also available are specialized physical IPs-TCAMs, Multiport Register Files, Customizable Data path, Custom PDK & PCELL for Mixed Signal IC design and SoC hardening solutions from RTL2GDSII. Having mastered the hash engine

in FinFET process, DXCorr offers a full custom double SHA256 ASIC IP for faster Bitcoin mining.

In the space of Deep Learning Accelerators(DLA), DXCorr’s Neural Compiler helps architects, designers and implementation teams build quickest time-to-market Deep Learning chips with predictable accuracy and performance targets.

DXCorr provides very specialized standard cell solutions. “We provide highly targeted solutions to meet unique power and performance requirements. We analyze current performance issues and augment existing libraries with a set of ‘kicker’ cells for significant performance and power improvement” adjoins Nirmalya.

DXCorr develops various inhouse tools that push the boundaries of the design process

Utilizing DXCorr's deep expertise, advanced tools, Industry veterans and sharp young talent, DXCorr develops High Performance and High Density SRAMs and MRAMs. Working on 7nm & 14nm FinFET, 22nm & 12nm FDSOI, 28nm & 40nm low power process nodes, DXCorr resolves the conflict in concurrent read & concurrent write operations in two port SRAMs. Power efficient, high speed binary and ternary CAMs helps clients stand out in a market that craves faster networks and more efficient processors. An in depth understanding of custom design allows DXCorr to improve the performance of various Custom Logic and Arithmetic function blocks at various process nodes.

Open mindedness and Innovation
Rather than focus on merely churning out serviceable designs, the emphasis is to innovate at every step. “Since innovation thrives in an ecosystem of unrestricted thought our engineers are encouraged to find out-of-the-box solutions to problems. We operate in an R&D mode thus amplifying free flow of ideas and independent thought,”adds Nirmalya.

We are busy foreseeing and solving problems yet to be encountered in relatively uncharted areas such as Artificial Intelligence and Machine Learning. This open-mindedness to embrace evolving subdomains of VLSI results in a redefining of previously held notions of ‘Design and Development'. Consequently, preconceived notions are challenged and out of this eternal churn comes a wellspring of fresh and innovative ideas.

“We’re ready for the future, and can’t wait to meet it,” signs off Nirmalya.