The era of miniaturization process has transformed the overall ASIC design cycle for the efficient high speed and low power designs along with implementation of SOC. Today, highly complex ASIC design is done at ease only because of the evolving widgets & technologies in the semiconductor industry, which was not possible a few years ago. In this bulging industry, everyone wants to get best PPAL (Power, Performance, Area, and Leakage key metric for an SOC/ASIC design) and attain it in the least possible time. With in-house software reducing the layout generation time and the design team working to provide the best PPAL by doing different optimization analysis, DXCorr joins the game providing the industry’s leading-edge custom physical IP solutions in 40nm, 28nm and 16/14nm process nodes. From complex ASIC solutions to hardening of SoC cores, DXCorr (Est. 2005) as a part of GF22FDX ecosystem offers the highest quality design service enabling its clients to achieve significant time-to-market and performance advantage in the most cost-effective manner.

As a part of ASIC/SOC design services, DXCorr offers solutions through out the entire gamut of the design space, starting from frontend to backend and finally

finishing up the chip for delivery. The front-end verification is a mixture of simulation, Static & Dynamic formal verification, Assertion-based verification and theorem proving. At the backend, the tools guide in floor planning, to be ready for place-and-route flow. Finally, a physically (DRC/LVS, Antenna, timing, Noise, &EM/IR) and functionally (formal, &EM/IR) verified tape-out-ready GDSII are operated to finish the chip tape-out.

Utilizing its deep engineering expertise combined with best-in-class tools, DXCorr develops high performance and high density SRAMs

The Advanced Portfolio
Developed by DXCorr’s Circuit & Layout team with the help of efficient in-house tools developed by CAD team, the advanced custom Physical IP portfolio covers physical IP blocks such as SRAM & ROM, standard cells and I/Os for most of the building blocks of SOC design, specialized physical IPs-TCAMs, multiport register files, customizable data-path, custom PDK & PCELL for mixed signal IC design and SOC hardening solutions from RTL2GDSII. Having mastered the hash engine in FinFET process, DXCorr is working on full custom double-SHA256 ASIC IP for Bitcoin mining, which helps crypto-currency miners mine Bitcoins faster, a task that gets harder with increasing mining complexity.

The combination of DXCorr’s highly optimized physical IP, specific custom block and its expert physical design teams

provide exceptional results.“While other IP vendors provide generic ‘one size fits all’ solutions, we believe that the client’s IP should be as unique as their design and we build exactly what is needed for them to compete and win in their market,” asserts Nirmalya Ghosh, CEO, DXCorr.

Utilizing its deep engineering expertise combined with best-in-class tools, DXCorr develops high performance and high density SRAMs. Working on 14nm FinFET technologies, 22nm and 12nm FDSOI, 28nm-low-power and 40nm-low-power process nodes, DXCorr resolves the conflict in concurrent write operations in dual port SRAMs. The power-efficient, high-speed Binary and Ternary CAMs make clients competent in a market seeking faster networks and further efficient processors. DXCorr provides standard cell solutions that make its customer’s designs stand out. “We provide highly targeted solutions to meet unique performance requirements, analyze current performance issues & augment existing library with a set of ‘kicker’ cells for a significant performance improvement,” adjoins Nirmalya.

QA: Quality Assurance
The quality management team responsible for clients’ issues raised at different level of abstraction Development time, Pre release QA and Post release QA, makes sure that all deliveries go through rigorous QA check for all the physical and frontend views as well as the verification of DFM rules. Incorporating incessant innovations in Circuit Design, Layout & P&R, DXCorr rides an assertive growth path complying with all the export control laws that regulate intellectual property with respect to its designs as well as its customer’s design.